1. Field of the Invention
The present invention relates to the structure of complementary metal-insulator semiconductor (hereinafter referred to as "C-MIS") transistors having deep and narrow ditches, that is, so-called trench isolation structure, and to the method of making such type of transistors.
2. Prior Art
The conventional isolation region of complementary metal oxide semiconductor (hereinafter referred to as "CMOS") device is formed generally by selective oxidization of semiconductor substrate surface (i.e. LOCOS). However, the minimum area dimension of the conventional isolation region is limited to such extent as to restrict higher integration density of the integrated circuit. In order to eliminate such limitation, another isolation method utilizing a deep and narrow ditch (trench) has been proposed. However, this method has failed to suppress a leak of electric current between N-type metal oxide semiconductor (hereinafter referred to as "NMOS") transistor and P-type metal oxide semiconductor (hereinafter referred to as "PMOS") transistor. Normally, a field-doped region is formed on the bottom of trench so as to suppress the leak. However, the smaller the width of trench, the smaller the effect of field-doped region. In addition, when trying to form another field-doped region on the inner sidewalls of trench, this causes a fabrication problem. Since the field-doping is normally carried out by ion implantation, it is difficult to implant ions into the inner sidewalls of trench.